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The Challenge of High-Speed PCB Stackup Design

Jarnistech > High Speed PCB > The Challenge of High-Speed PCB Stackup Design
Blue High Speed 4 Layer PCB

In the realm of high-speed PCB design, achieving perfection in every aspect can be challenging due to practical limitations. Despite this, it is often possible to create a stackup that is sufficiently effective, even for high-speed applications. This involves striking a balance between various engineering constraints, functional requirements, and the imperative of ensuring signal and power integrity, as well as compliance with EMC standards.

While there are many established guidelines for high-speed design, there are certain nuances in stackup construction that are frequently overlooked in the board building process. By adopting a broader engineering perspective, we can address these overlooked factors and enhance the overall performance of our designs. This approach takes into account the multitude of constraints that influence product development and emphasizes the importance of considering all aspects of a design to ensure its success.

High Speed PCB Stackup: Converting Limitations into Design Considerations

When approaching high-speed PCB design from an engineering perspective, it is essential to begin by outlining a comprehensive list of constraints and functional requirements for the system being developed. Typically, this process commences with the selection of a specific component, such as a processor and its associated peripherals (CPU or FPGA, memories, specialty chips, etc.), especially in client projects.

A sample set of constraints that are commonly encountered in high-speed PCB design includes parameters such as the pin count and lead size of primary components (e.g., BGA), the number of I/Os in large components influencing layer count, interface count, the quantity of signals in each interface, target board thickness (potentially non-standard), and desired loss levels relative to board size.

Starting with these argument is crucial as it allows for alignment with functional requirements dictated by the selected components, which in turn influence factors like I/O count and signal count. Prior to exploring off-the-shelf materials or adopting a standard stackup, it is imperative to address the considerations outlined above to ensure that the design is tailored to meet the specific needs of the system being developed.

The Challenge of High-Speed PCB Stackup Design

As we progress to advanced boards with a high layer count, there is a notable intersection between HDI (High-Density Interconnect) materials and high-speed functionality. HDI stackups designed to accommodate controlled impedance and facilitate high-speed interfaces can present challenges related to linewidths and spacings, often necessitating non-standard processing methods. The following process will delve into the design complexities associated with these challenges and highlight the Design for Manufacturability (DFM) considerations essential for the successful realization of these products.

1.Board and Layer Thickness as Starting Points

In high-speed PCBs with elevated I/O counts, the thickness of the layers plays a crucial role, often necessitating very thin layers. There is a common misconception that a high I/O count mandates the use of a larger-than-standard board thickness due to the increased layer count. However, this is not always the case, as there are materials available that enable designers to maintain the standard board size target while utilizing low layer thicknesses.

The significance of layer thickness in high-speed designs lies in its impact on the required linewidth to achieve a specific impedance target. As the thickness of a signal layer decreases, the corresponding line width for impedance-controlled signals also decreases proportionally. This relationship underscores the importance of carefully considering layer thickness in high-speed PCB designs to ensure precise impedance control and optimal signal integrity.

● Exploring Trace Width Considerations on Thin Dielectrics

When faced with constraints on board thickness and the necessity to achieve thinner layer thicknesses in high-speed PCB designs, there may arise challenges in maintaining linewidths within the capabilities of standard fabrication or HDI production processes. However, exploring alternative materials can offer a solution to achieve reduced thickness without compromising on required linewidths. One potential avenue to address this issue is the utilization of low-Dk (dielectric constant) materials.

By incorporating low-Dk materials in the PCB design, designers can achieve the desired reduction in layer thickness without the need to scale down the linewidths beyond the capabilities of the manufacturing processes. These materials exhibit lower dielectric constants, which can help in maintaining signal integrity and impedance control while enabling the attainment of thinner layer configurations. By leveraging the properties of low-Dk materials, designers can navigate challenges related to layer thickness constraints and linewidth requirements in high-speed PCB designs, ultimately optimizing performance and reliability.

2.Choosing Between PTFE and Low-Dk Materials: When to Opt for Each Option

It is a common misconception perpetuated by some individuals claiming expertise that low-Dk laminates or PTFE substrates should always be employed in high-speed PCB designs as a universal rule. However, it is imperative to recognize that high-speed PCB applications encompass a diverse range of data rates, edge rates, bandwidths, and trace widths. While certain designs may fall under the category of “high-speed,” they may not necessarily require the use of a low-Dk laminate. Similarly, in the realm of HDI designs, there are instances where a low-Dk laminate is utilized, but not solely for the purpose of achieving low insertion loss.

Among the most frequently cited low-Dk materials is ceramic-filled PTFE, which offers a wide spectrum of material options. The dielectric constant (Dk) of PTFE-based materials can be tailored through the incorporation of ceramic fillers, resulting in a diverse range of Dk values. For example, cured PTFE substrates can exhibit Dk values spanning from approximately 3 to around 10, all while maintaining lower losses compared to standard FR4 laminates. It is essential to consider the specific requirements and characteristics of each high-speed PCB design to determine the most suitable material options, rather than adhering to blanket recommendations regarding low-Dk laminates.

3.Managing Loss and Dk Value in PCB Design

In situations where layer thickness is minimized, the required linewidth to achieve a specific impedance will also be reduced. If the linewidth becomes too small, processing challenges can arise, leading to increased costs. This underscores the significance of the first point mentioned above; lower dielectric constant (Dk) values allow for wider linewidths within a given substrate thickness, aiding in maintaining manufacturability and controlling costs.

To strike a balance between low loss and high Dk, there are materials available with Dk values ranging from 3.5 to 4, exhibiting lower loss tangents compared to standard FR4 laminates. Leading companies such as Rogers and Isola offer these laminates, with another material option from ITEQ boasting a loss tangent of approximately 0.01.

When low-Dk materials are required in high-speed PCBs at the HDI level, they often necessitate glass reinforcement. This reinforcement can be achieved through spread glass at around 5 mils thickness, although thinner layers may require a loose weave for adequate reinforcement. The use of spread glass reinforcement aims to minimize skew accumulation, particularly when the material is utilized for signal layers. The primary rationale behind this approach is to enhance manufacturability:

● Unreinforced PTFE laminates, especially in thin layers, exhibit high flexibility, which can make handling and stacking them in a PCB assembly challenging.

● Due to the implications outlined in point #1, there may be potential misregistration issues during the layer stackup process in standard manufacturing procedures.

4.Why Using of Low-Dk Materials in RF Design

PTFE laminates are widely favored within the RF community for their exceptional performance characteristics, although the precise reasons for their popularity may not be fully understood by digital designers. One of the primary factors driving the preference for PTFE laminates, such as the RO3000 series materials, is their remarkably low loss properties.

In RF board design, the selection of dielectric constant (Dk) values plays a crucial role in achieving a balance between circuit size and loss. It is worth noting that certain high-Dk PTFE laminates exhibit lower losses than standard FR4 materials when considering the imaginary part of the dielectric constant. While higher Dk values facilitate smaller circuits at lower frequencies, lower Dk values are often preferred for ensuring manufacturability at higher frequencies, such as in radar applications.

Moreover, the utilization of PTFE laminates in RF boards is also driven by the longer channel lengths typically present in digital boards, where propagation-related loss mechanisms, including dielectric loss and copper roughness loss, become predominant. Modern low-Dk PTFE materials are characterized by extremely low loss tangents, resulting in minimal dielectric loss. Additionally, these laminates can accommodate very low roughness VLP copper, effectively reducing copper losses compared to standard electrodeposited copper. The combination of low dielectric loss and reduced copper losses makes PTFE laminates an excellent choice for RF applications.

5.Embedded Capacitance Materials (ECM)

For optimal power integrity, careful selection of the dielectric material between power and ground plane pairs is crucial. Contrary to conventional belief regarding low-loss, low-dielectric constant (Dk) materials, the dielectric in this context should exhibit high Dk and high losses. Additionally, minimizing the thickness of these layers is advantageous.

The industry has developed ultrathin, high-Dk materials that can be integrated into resin-fiberglass systems. These embedded capacitance materials (ECMs) are not essential for power integrity but enhance high-speed PCBs with numerous layers. This is attributed to three primary factors:

● High Dk Provides Enhanced Plane Capacitance: High Dk materials increase plane capacitance, reducing power plane resonances.

● Thinner ECM Layers Increase Plane Capacitance: Thin ECM layers provide greater plane capacitance due to the increased number of planes within a given thickness.

● High Losses Dampen Power Fluctuations: The high losses in ECM layers rapidly mitigate power fluctuations, stabilizing the power supply.

The Dk values of ECM materials typically range from approximately 4 to 10 between 100 MHz and 1 GHz, aligning with the frequency band where plane capacitance is desirable to dampen resonances and compensate for insufficient on-chip or in-package capacitance. The thickness of these materials is typically in the micron range.

Notable manufacturers of ECM materials include 3M and DuPont, with FaradFlex being another recognized brand. The combination of high Dk and thinness enables these materials to be incorporated into stackups with high layer counts, further enhancing power integrity in complex PCB designs.


In high-speed PCB stackup design, the process of creating the stackup is typically the final step. However, greater emphasis should be placed on determining the appropriate layer counts and their respective physical properties in relation to component lead sizes and fanouts. This approach allows for more informed material selection for signal layers and evaluation of embedded capacitance materials for power/ground plane pairs.

For simpler designs, such as 4-layer high-speed PCBs, the primary considerations are limited to outer layer thickness and dielectric constant (Dk) value. These factors directly impact the trace width required to achieve the desired single-ended impedance, as well as the spacing necessary to maintain a specific differential impedance target.

By prioritizing layer counts, material selection, and impedance control, designers can optimize the performance and signal integrity of their high-speed PCBs.

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